FIG. 1 is an example of one type of PoDL system to which the present invention will be compared.
A PHY 10 outputs differential data and receives differential data via a conventional Media Dependent Interface (MDI) connector 12 coupled to wires 14 and 16 of a twisted wire pair. A conventional powered device (PD) is coupled to the other end of the wires 14/16. The PHY 10 represents the physical layer in the OSI model (Open Systems Interconnection model) and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is a term of art and is defined by various IEEE standards, depending on the particular application. The PHY 10 is typically an integrated circuit. A digital processor (not shown) is coupled to the PHY 10 for processing the data.
The PHY 10 is connected to the MDI connector 12 via a common mode choke (CMC) 18, AC coupling capacitors C1 and C2, and a galvanic isolation transformer 20. The polarities of the windings are designated by the dots.
The CMC 18 is an in-line transformer with two windings, where each winding is in series with a wire in the twisted wire pair. As shown by the dots on the CMC 18 windings, the windings have the same polarity, so the magnetic fields generated by a differential mode signal are substantially cancelled out. Thus, the CMC 18 presents little inductance or impedance to differential-mode currents. Common mode currents, such as ambient noise in the wire pair, however, see a high impedance due to the combined inductances of the windings.
The CMC 18 ideally eliminates or greatly attenuates common mode RF noise while providing no loss for the differential or DC voltage signals.
The transformer 20 provides added DC isolation and common mode noise attenuation for the PHY 10. The secondary winding may be center tapped to provide a ground reference.
Therefore, there is little attenuation of differential mode signals between the PHY 10 and the wires 14 and 16, while there is very high attenuation of common mode noise and DC power between the PHY 10 and the wires 14 and 16.
A differential mode choke (DMC) 22 is coupled between the MDI connector 12 and a DC power supply 24. The power supply 24 has a low output impedance as is characteristic of a voltage source. The DMC 22 has windings with opposite polarities (dots on opposite ends). The DMC 22 presents a high impedance to AC differential mode signals while it shunts the common mode signals to the power supply 24 due to its low impedance to common mode signals. Therefore, the combination of the CMC 18 and the DMC 22 can substantially remove AC common mode noise that has been coupled to the wire pair.
A termination circuit 25 comprises resistors R1 and R2 and capacitors C3 and C4 coupled to the wires 14 and 16, via the MDI connector 12, to eliminate reflections of the common mode noise on the twisted wire pair. The termination circuit 25 is generally designed to match the common mode impedance of the wire pair to minimize common mode reflectance.
Although the circuit of FIG. 1 works well, it requires three relatively expensive and large components: transformer 20, CMC 18, and DMC 22. Further, if these components have mismatched windings, mode conversion may occur, leading to data errors. The two AC-coupling capacitors C1 and C2 also add size and expense.
What is needed is a PoDL circuit that uses fewer components than the circuit of FIG. 1, so is potentially smaller and less expensive, while achieving a similar level of galvanic isolation and common mode noise attenuation with high DC power coupling efficiency.